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integrated circuit systems, inc. ICS952801 advance information 0719?01/22/03 pin configuration recommended application: sis755/760 style chipset for amd k8 processor output features: 2 - pairs of differential push-pull k8cpu outputs 8 - pciclk @ 3.3v 2 - agpclk @ 3.3v 3 - ref @ 3.3v 2 - zclk @ 3.3v 1 - 24_48mhz @ 3.3v 1 - 48mhz @ 3.3v key specifications: cpu output jitter <250ps agp output jitter <250ps zclk output jitter <250ps pci output jitter <500ps programmable timing control hub? for k8? processor functionality features/benefits: quadromtm frequency selection. selectable synchronous/asynchronous agp/pci/zclk frequency linear programmable cpu output frequency. linear programmable agp/pci output frequency. programmable output divider ratios. programmable output rise/fall time. programmable output skew. programmable spread percentage for emi control. watchdog timer technology to reset system if system malfunctions. programmable watch dog safe frequency. support i2c index read/write and block read/write operations. uses external 14.318mhz referience input. advance information documents contain information on products in the formative or design phase development. characteristic data and other specific ations are design goals. ics reserves the right to change or discontinue these products without notice. third party brands and names are the property of their respective owners. vddref 1 48 cpu_stop#* **fs0/ref0 2 47 gndcpu **fs1/ref1 3 46 cpuclk8t1 **fs2/ref2 4 45 cpuclk8c1 gndref 5 44 vddcpu x1 6 43 vddcpu x2 7 42 cpuclk8t0 gndz 8 41 cpuclk8c0 zclk0 9 40 gndcpu zclk1 10 39 agnd vddz 11 38 avdd *pci_stop# 12 37 pd#* **fs3/pciclk_f0 13 36 gndagp **fs4/pciclk_f1 14 35 agpclk0 vddpci 15 34 agpclk1 gndpci 16 33 vddagp pciclk0 17 32 sclk pciclk1 18 31 avdd48 pciclk2 19 30 48mhz pciclk3 20 29 24_48mhz/sel24_48mhz* pciclk4 21 28 gnd48 pciclk5 22 27 sdata gndpci 23 26 pciclk7 vddpci 24 25 pciclk6 48-ssop * internal pull-up resistor ** internal pull-down resistor ICS952801 bit4 bit3 bit2 bit1 bit0 cpu zclk agp pci fs4fs3fs2fs1fs0 mhz mhz mhz mhz 0 0 0 0 0 200.00 66.67 66.67 33.33 0 0 0 0 1 200.00 100.00 66.67 33.33 0 0 0 1 0 200.00 133.33 66.67 33.33 0 0 0 1 1 200.00 166.67 66.67 33.33 0 0 1 0 0 233.33 66.67 66.67 33.33 0 0 1 0 1 233.33 93.33 66.67 33.33 0 0 1 1 0 233.33 133.33 66.67 33.33 0 0 1 1 1 233.33 175.00 70.00 35.00 0 1 0 0 0 266.67 66.67 66.67 33.33 0 1 0 0 1 266.67 106.67 66.67 33.33 0 1 0 1 0 266.67 133.33 66.67 33.33 0 1 0 1 1 266.67 160.00 66.67 33.33 0 1 1 0 0 293.34 73.34 73.33 36.66 0 1 1 0 1 293.34 117.34 73.33 36.66 0 1 1 1 0 293.34 146.66 73.33 36.66 0 1 1 1 1 293.34 176.00 73.33 36.66 10000 133.33 66.67 66.67 33.33 10001 133.33 100.00 66.67 33.33 10010 133.33 133.33 66.67 33.33 10011 133.33 166.67 66.67 33.33 1 0 1 0 0 166.67 66.67 66.67 33.33 1 0 1 0 1 166.67 100.00 66.67 33.33 1 0 1 1 0 166.67 133.33 66.67 33.33 1 0 1 1 1 166.67 166.67 66.67 33.33 1 1 0 0 0 202.00 67.34 67.33 33.66 1 1 0 0 1 202.00 101.00 67.33 33.66 1 1 0 1 0 202.00 134.66 67.33 33.66 1 1 0 1 1 202.00 168.34 67.33 33.66 1 1 1 0 0 220.00 73.34 73.33 36.66 1 1 1 0 1 220.00 110.00 73.33 36.66 1 1 1 1 0 220.00 146.66 73.33 36.66 11111 220.00 183.34 73.33 36.66
2 integrated circuit systems, inc. ICS952801 advance information 0719?01/22/03 the ICS952801 is a two chip clock solution for desktop designs using sis 755/760 style chipsets. when used with a zero delay buffer such as the ics9179-16 for pc133 or the ics93735 for ddr applications it provides all the necessary clocks signals for such a system. the ICS952801 is part of a whole new line of ics clock generators and buffers called tch? (timing control hub). ics is the first to introduce a whole product line which offers full programmability and flexibility on a single clock device. employing t he use of a serially programmable i 2 c interface, this device can adjust the output clocks by configuring the frequency setting, the output divider ratios, selecting the ideal spread percentage, the output skew, the output strength, and enabling/disabling each individual output clock. tch also incorporates ics's watchdog timer technology and a reset feature to provide a safe setting under unstable system conditions. m/n control can configure output frequency with resolution up to 0.1mhz increment. general description block diagram power groups vdd gnd 1 5 ref output, crystal 31 28 24/48mhz, fix analog, fix digital 38 36 cpu pll, cpu analog, mclk pin number description cpuclk8t (1:0) agpclk (1:0) pciclk (5:0) pciclkf (1:0) zclk (1:0) cpuclk8c (1:0) pll2 frequency dividers programmable spread pll1 programmable frequency dividers stop logic 48mhz 24_48mhz x1 x2 xtal pd# cpu_stop# pci_stop# fs (4:0) sel24_48mhz control logic ref (2:0)
3 integrated circuit systems, inc. ICS952801 advance information 0719?01/22/03 pin description pin pin pin # name type 1 vddref pwr ref, xtal power supply, nominal 3.3v 2 **fs0/ref0 i/o frequency select latch input pin / 14.318 mhz reference clock. 3 **fs1/ref1 i/o frequency select latch input pin / 14.318 mhz reference clock. 4 **fs2/ref2 i/o frequency select latch input pin / 14.318 mhz reference clock. 5 gndref pwr ground pin for the ref outputs. 6 x1 in crystal input,nominally 14.318mhz. 7 x2 out crystal output, nominally 14.318mhz 8 gndz pwr ground pin for the zclk outputs 9 zclk0 out 3.3v hyperzip clock output. 10 zclk1 out 3.3v hyperzip clock output. 11 vddz pwr power supply for zclk clocks, nominal 3.3v 12 *pci_stop# i/o pci clock output, this output is activated by the mode selection pin / stops all pciclks besides the pciclk_f clocks at logic 0 level, when input low. 13 **fs3/pciclk_f0 i/o frequency select latch input pin / 3.3v pci free running clock output. 14 **fs4/pciclk_f1 i/o frequency select latch input pin / 3.3v pci free running clock output. 15 vddpci pwr power supply for pci clocks, nominal 3.3v 16 gndpci pwr ground pin for the pci outputs 17 pciclk0 out pci clock output. 18 pciclk1 out pci clock output. 19 pciclk2 out pci clock output. 20 pciclk3 out pci clock output. 21 pciclk4 out pci clock output. 22 pciclk5 out pci clock output. 23 gndpci pwr ground pin for the pci outputs 24 vddpci pwr power supply for pci clocks, nominal 3.3v 25 pciclk6 out pci clock output. 26 pciclk7 out pci clock output. 27 sdata i/o data pin for i2c circuitry 5v tolerant 28 gnd48 pwr ground pin for the 48mhz outputs 29 24_48mhz/sel24_48mhz* i/o 24/48mhz clock output / latched select input for 24/48mhz output. 0=24mhz, 1 = 48mhz. 30 48mhz out 48mhz clock output. 31 avdd48 pwr power for 24/48mhz outputs and fixed pll core, nominal 3.3v 32 sclk in clock pin of i2c circuitry 5v tolerant 33 vddagp pwr power supply for agp clocks, nominal 3.3v 34 agpclk1 out agp clock output 35 agpclk0 out agp clock output 36 gndagp pwr ground pin for the agp outputs 37 pd#* in asynchronous active low input pin used to power down the device into a low power state. the internal clocks are disabled and the vco and the crystal are stopped. the latency of the power down will not be greater than 1.8ms. 38 avdd pwr 3.3v analog power pin for core pll 39 agnd pwr analog ground pin for core pll 40 gndcpu pwr ground pin for the cpu outputs 41 cpuclk8c0 out "complementary" clocks of differential 3.3v push-pull k8 pair. 42 cpuclk8t0 out "true" clocks of differential 3.3v push-pull k8 pair. 43 vddcpu pwr supply for cpu clocks, 3.3v nominal 44 vddcpu pwr supply for cpu clocks, 3.3v nominal 45 cpuclk8c1 out "complementary" clocks of differential 3.3v push-pull k8 pair. 46 cpuclk8t1 out "true" clocks of differential 3.3v push-pull k8 pair. 47 gndcpu pwr ground pin for the cpu outputs 48 cpu_stop#* in stops all cpuclk besides the free running clocks * internal pull-up resistor ** internal pull-down resistor description
4 integrated circuit systems, inc. ICS952801 advance information 0719?01/22/03 general i 2 c serial interface information for the ICS952801 how to write: ? controller (host) sends a start bit. controller (host) sends the write address d2 (h) ics clock will acknowledge controller (host) sends the begining byte location = n ics clock will acknowledge controller (host) sends the data byte count = x ics clock will acknowledge controller (host) starts sending byte n through byte n + x -1 (see note 2) ics clock will acknowledge each byte one at a time controller (host) sends a stop bit how to read: controller (host) will send start bit. controller (host) sends the write address d2 (h) ics clock will acknowledge controller (host) sends the begining byte location = n ics clock will acknowledge controller (host) will send a separate start bit. controller (host) sends the read address d3 (h) ics clock will acknowledge ics clock will send the data byte count = x ics clock sends byte n + x -1 ics clock sends byte 0 through byte x (if x (h) was written to byte 8) . controller (host) will need to acknowledge each byte controllor (host) will send a not acknowledge bit controller (host) will send a stop bit ics (slave/receiver) t wr ack ack ack ack ack p stop bit x byte index block write operation slave address d2 (h) beginning byte = n write start bit controller (host) byte n + x - 1 data byte count = x beginning byte n t start bit wr write rt repeat start rd read beginning byte n byte n + x - 1 n not acknowledge pstop bit slave address d3 (h) index block read operation slave address d2 (h) beginning byte = n ack ack data byte count = x ack ics (slave/receiver) controller (host) x byte ack ack
5 integrated circuit systems, inc. ICS952801 advance information 0719?01/22/03 table1: quadrom frequency selection table bit6 bit5 bit4 bit3 bit2 bit1 bit0 cpu zclk agp pci spread x x fs4 fs3 fs2 fs1 fs0 mhz mhz mhz mhz % 0000000 200.00 66.67 66.67 33.33 0.3% center 0 0 0 0 0 0 1 200.00 100.00 66.67 33.33 0.3% center 0 0 0 0 0 1 0 200.00 133.33 66.67 33.33 0.3% center 0 0 0 0 0 1 1 200.00 166.67 66.67 33.33 0.3% center 0 0 0 0 1 0 0 233.33 66.67 66.67 33.33 0.3% center 0 0 0 0 1 0 1 233.33 93.33 66.67 33.33 0.3% center 0 0 0 0 1 1 0 233.33 133.33 66.67 33.33 0.3% center 0 0 0 0 1 1 1 233.33 175.00 70.00 35.00 0.3% center 0 0 0 1 0 0 0 266.67 66.67 66.67 33.33 spread off 0 0 0 1 0 0 1 266.67 106.67 66.67 33.33 spread off 0 0 0 1 0 1 0 266.67 133.33 66.67 33.33 spread off 0 0 0 1 0 1 1 266.67 160.00 66.67 33.33 spread off 0 0 0 1 1 0 0 293.34 73.34 73.33 36.66 spread off 0 0 0 1 1 0 1 293.34 117.34 73.33 36.66 spread off 0 0 0 1 1 1 0 293.34 146.66 73.33 36.66 spread off 0 0 0 1 1 1 1 293.34 176.00 73.33 36.66 spread off 0 0 1 0 0 0 0 133.33 66.67 66.67 33.33 0.3% center 0 0 1 0 0 0 1 133.33 100.00 66.67 33.33 0.3% center 0 0 1 0 0 1 0 133.33 133.33 66.67 33.33 0.3% center 0 0 1 0 0 1 1 133.33 166.67 66.67 33.33 0.3% center 0 0 1 0 1 0 0 166.67 66.67 66.67 33.33 0.3% center 0 0 1 0 1 0 1 166.67 100.00 66.67 33.33 0.3% center 0 0 1 0 1 1 0 166.67 133.33 66.67 33.33 0.3% center 0 0 1 0 1 1 1 166.67 166.67 66.67 33.33 0.3% center 0 0 1 1 0 0 0 202.00 67.34 67.33 33.66 b24b2:1 =11 0 0 1 1 0 0 1 202.00 101.00 67.33 33.66 b24b2:1 =11 0 0 1 1 0 1 0 202.00 134.66 67.33 33.66 b24b2:1 =11 0 0 1 1 0 1 1 202.00 168.34 67.33 33.66 b24b2:1 =11 0 0 1 1 1 0 0 220.00 73.34 73.33 36.66 spread off 0 0 1 1 1 0 1 220.00 110.00 73.33 36.66 spread off 0 0 1 1 1 1 0 220.00 146.66 73.33 36.66 spread off 0011111 220.00 183.34 73.33 36.66 spread off
6 integrated circuit systems, inc. ICS952801 advance information 0719?01/22/03 table1: quadrom frequency selection table continued bit6 bit5 bit4 bit3 bit2 bit1 bit0 cpu zclk agp pci spread x x fs4 fs3 fs2 fs1 fs0 mhz mhz mhz mhz % 0 1 0 0 0 0 0 206.00 68.67 68.67 34.33 spread off 0 1 0 0 0 0 1 206.00 103.00 68.67 34.33 spread off 0 1 0 0 0 1 0 206.00 137.33 68.67 34.33 spread off 0 1 0 0 0 1 1 206.00 171.67 68.67 34.33 spread off 0 1 0 0 1 0 0 240.33 68.67 68.67 34.33 spread off 0 1 0 0 1 0 1 240.33 96.13 68.67 34.33 spread off 0 1 0 0 1 1 0 240.33 137.33 68.67 34.33 spread off 0 1 0 0 1 1 1 240.33 180.25 72.10 36.05 spread off 0 1 0 1 0 0 0 274.67 68.67 68.67 34.33 spread off 0 1 0 1 0 0 1 274.67 109.87 68.67 34.33 spread off 0 1 0 1 0 1 0 274.67 137.33 68.67 34.33 spread off 0 1 0 1 0 1 1 274.67 164.80 68.67 34.33 spread off 0 1 0 1 1 0 0 302.14 75.54 75.53 37.76 spread off 0 1 0 1 1 0 1 302.14 120.86 75.53 37.76 spread off 0 1 0 1 1 1 0 302.14 151.06 75.53 37.76 spread off 0 1 0 1 1 1 1 302.14 181.28 75.53 37.76 spread off 0 1 1 0 0 0 0 137.33 68.67 68.67 34.33 spread off 0 1 1 0 0 0 1 137.33 103.00 68.67 34.33 spread off 0 1 1 0 0 1 0 137.33 137.33 68.67 34.33 spread off 0 1 1 0 0 1 1 137.33 171.67 68.67 34.33 spread off 0 1 1 0 1 0 0 171.67 68.67 68.67 34.33 spread off 0 1 1 0 1 0 1 171.67 103.00 68.67 34.33 spread off 0 1 1 0 1 1 0 171.67 137.33 68.67 34.33 spread off 0 1 1 0 1 1 1 171.67 171.67 68.67 34.33 spread off 0 1 1 1 0 0 0 208.06 69.36 69.35 34.67 spread off 0 1 1 1 0 0 1 208.06 104.03 69.35 34.67 spread off 0 1 1 1 0 1 0 208.06 138.70 69.35 34.67 spread off 0 1 1 1 0 1 1 208.06 173.39 69.35 34.67 spread off 0 1 1 1 1 0 0 226.60 75.54 75.53 37.76 spread off 0 1 1 1 1 0 1 226.60 113.30 75.53 37.76 spread off 0 1 1 1 1 1 0 226.60 151.06 75.53 37.76 spread off 0 1 1 1 1 1 1 226.60 188.84 75.53 37.76 spread off
7 integrated circuit systems, inc. ICS952801 advance information 0719?01/22/03 table1: quadrom frequency selection table continued bit6 bit5 bit4 bit3 bit2 bit1 bit0 cpu zclk agp pci spread x x fs4 fs3 fs2 fs1 fs0 mhz mhz mhz mhz % 1 0 0 0 0 0 0 214.00 71.34 71.33 35.66 spread off 1 0 0 0 0 0 1 214.00 107.00 71.33 35.66 spread off 1 0 0 0 0 1 0 214.00 142.66 71.33 35.66 spread off 1 0 0 0 0 1 1 214.00 178.34 71.33 35.66 spread off 1 0 0 0 1 0 0 249.66 71.33 71.33 35.66 spread off 1 0 0 0 1 0 1 249.66 99.86 71.33 35.66 spread off 1 0 0 0 1 1 0 249.66 142.66 71.33 35.66 spread off 1 0 0 0 1 1 1 249.66 187.25 74.90 37.45 spread off 1 0 0 1 0 0 0 285.34 71.34 71.33 35.66 spread off 1 0 0 1 0 0 1 285.34 114.14 71.33 35.66 spread off 1 0 0 1 0 1 0 285.34 142.66 71.33 35.66 spread off 1 0 0 1 0 1 1 285.34 171.20 71.33 35.66 spread off 1 0 0 1 1 0 0 313.87 78.47 78.47 39.23 spread off 1 0 0 1 1 0 1 313.87 125.55 78.47 39.23 spread off 1 0 0 1 1 1 0 313.87 156.93 78.47 39.23 spread off 1 0 0 1 1 1 1 313.87 188.32 78.47 39.23 spread off 1 0 1 0 0 0 0 142.66 71.34 71.33 35.66 spread off 1 0 1 0 0 0 1 142.66 107.00 71.33 35.66 spread off 1 0 1 0 0 1 0 142.66 142.66 71.33 35.66 spread off 1 0 1 0 0 1 1 142.66 178.34 71.33 35.66 spread off 1 0 1 0 1 0 0 178.34 71.34 71.33 35.66 spread off 1 0 1 0 1 0 1 178.34 107.00 71.33 35.66 spread off 1 0 1 0 1 1 0 178.34 142.66 71.33 35.66 spread off 1 0 1 0 1 1 1 178.34 178.34 71.33 35.66 spread off 1 0 1 1 0 0 0 216.14 72.05 72.05 36.02 spread off 1 0 1 1 0 0 1 216.14 108.07 72.05 36.02 spread off 1 0 1 1 0 1 0 216.14 144.09 72.05 36.02 spread off 1 0 1 1 0 1 1 216.14 180.12 72.05 36.02 spread off 1 0 1 1 1 0 0 235.40 78.47 78.47 39.23 spread off 1 0 1 1 1 0 1 235.40 117.70 78.47 39.23 spread off 1 0 1 1 1 1 0 235.40 156.93 78.47 39.23 spread off 1 0 1 1 1 1 1 235.40 196.17 78.47 39.23 spread off
8 integrated circuit systems, inc. ICS952801 advance information 0719?01/22/03 table1: quadrom frequency selection table continued bit6 bit5 bit4 bit3 bit2 bit1 bit0 cpu zclk agp pci spread x x fs4 fs3 fs2 fs1 fs0 mhz mhz mhz mhz % 1 1 0 0 0 0 0 220.00 73.34 73.33 36.66 spread off 1 1 0 0 0 0 1 220.00 110.00 73.33 36.66 spread off 1 1 0 0 0 1 0 220.00 146.66 73.33 36.66 spread off 1 1 0 0 0 1 1 220.00 183.34 73.33 36.66 spread off 1 1 0 0 1 0 0 256.66 73.33 73.33 36.66 spread off 1 1 0 0 1 0 1 256.66 102.66 73.33 36.66 spread off 1 1 0 0 1 1 0 256.66 146.66 73.33 36.66 spread off 1 1 0 0 1 1 1 256.66 192.50 77.00 38.50 spread off 1 1 0 1 0 0 0 293.34 73.34 73.33 36.66 spread off 1 1 0 1 0 0 1 293.34 117.34 73.33 36.66 spread off 1 1 0 1 0 1 0 293.34 146.66 73.33 36.66 spread off 1 1 0 1 0 1 1 293.34 176.00 73.33 36.66 spread off 1 1 0 1 1 0 0 322.67 80.67 80.67 40.33 spread off 1 1 0 1 1 0 1 322.67 129.07 80.67 40.33 spread off 1 1 0 1 1 1 0 322.67 161.33 80.67 40.33 spread off 1 1 0 1 1 1 1 322.67 193.60 80.67 40.33 spread off 1 1 1 0 0 0 0 146.66 73.34 73.33 36.66 spread off 1 1 1 0 0 0 1 146.66 110.00 73.33 36.66 spread off 1 1 1 0 0 1 0 146.66 146.66 73.33 36.66 spread off 1 1 1 0 0 1 1 146.66 183.34 73.33 36.66 spread off 1 1 1 0 1 0 0 183.34 73.34 73.33 36.66 spread off 1 1 1 0 1 0 1 183.34 110.00 73.33 36.66 spread off 1 1 1 0 1 1 0 183.34 146.66 73.33 36.66 spread off 1 1 1 0 1 1 1 183.34 183.34 73.33 36.66 spread off 1 1 1 1 0 0 0 222.20 74.07 74.07 37.03 spread off 1 1 1 1 0 0 1 222.20 111.10 74.07 37.03 spread off 1 1 1 1 0 1 0 222.20 148.13 74.07 37.03 spread off 1 1 1 1 0 1 1 222.20 185.17 74.07 37.03 spread off 1 1 1 1 1 0 0 242.00 80.67 80.67 40.33 spread off 1 1 1 1 1 0 1 242.00 121.00 80.67 40.33 spread off 1 1 1 1 1 1 0 242.00 161.33 80.67 40.33 spread off 1 1 1 1 1 1 1 242.00 201.67 80.67 40.33 spread off
9 integrated circuit systems, inc. ICS952801 advance information 0719?01/22/03 i 2 c table: function control register control function bit 7 pden pd# enable rw disable enable 1 bit 6 pciclk7 output control rw disable enable 1 bit 5 wds_en wd soft enable rw disable enable 1 bit 4 pciclk6 output control rw disable enable 1 bit 3 afs1 async rom sel_1 rw 0 bit 2 afs0 async rom sel_0 rw 0 bit 1 aen1 rw 0 bit 0 aen0 rw 0 zclk/agp/pci freq source select control see table 3: async z-clk frequency selection table see table 4 : zclk, agp & pci frequency source decode table - - - 25 - - 1pwd - 26 name pin # byte 0 type 0 table 3: asynchronous zclk frequency selection table table 4: zclk, agp & pci frequency source decode table b y te0 bit3 b y te0 bit2 zclk fre q uenc y b y te0 bit1 b y te0 bit0 zclk & agp & pci 0 0 64.01 0 0 see table 1, quadrom frequency table 0 1 72.01 0 1 n-pro g rammin g for agp/pci/zcl k 1 0 82.30 1 0 see table 1 for agp/pci, table 3 for zclk 1 1 144.02 1 1 n-pro g rammin g for agp/pci, table 3 for zclk i 2 c table: async n-programming frequency select register control function bit 7 n pll3 div7 rw - - 0 bit 6 n pll3 div6 rw - - 1 bit 5 n pll3 div5 rw - - 0 bit 4 n pll3 div4 rw - - 0 bit 3 n pll3 div3 rw - - 0 bit 2 n pll3 div2 rw - - 1 bit 1 n pll3 div1 rw - - 1 bit 0 n pll3 div0 rw - - 1 i 2 c table: reserved register control function bit 7 reserved reserved rw - - 1 bit 6 reserved reserved rw - - 1 bit 5 reserved reserved rw - - 1 bit 4 reserved reserved rw - - 1 bit 3 reserved reserved rw - - 1 bit 2 reserved reserved rw - - 1 bit 1 reserved reserved rw - - 1 bit 0 reserved reserved rw - - 1 the decimal representation of n pll2 div (7:0) + 8 is equal to vco divider value for pll2. default at power up = 66.67mhz - - name - - - 1 1pwd 0 type pwd 0 - - name type byte 2 - pin # - pin # - byte 1 - - - - -
10 integrated circuit systems, inc. ICS952801 advance information 0719?01/22/03 i 2 c table: reserved register control function bit 7 reserved reserved rw - - 1 bit 6 reserved reserved rw - - 1 bit 5 reserved reserved rw - - 1 bit 4 reserved reserved rw - - 1 bit 3 reserved reserved rw - - 1 bit 2 reserved reserved rw - - 1 bit 1 reserved reserved rw - - 1 bit 0 reserved reserved rw - - 1 i 2 c table: frequency select register control function bit 7 fs3 freq select bit 7 rw 0 bit 6 fs2 freq select bit 6 rw 0 bit 5 fs1 freq select bit 5 rw 0 bit 4 fs0 freq select bit 4 rw 0 bit 3 fs source frequency hw/iic select rw latch input iic 0 bit 2 fs4 freq select bit 2 rw 0 bit 1 ss_en spread enable rw off on 1 bit 0 outputs output control rw running tri-state 0 i 2 c table: read back register control function bit 7 wdhrb wd hard alarm status read back rnormalalarmx bit 6 wdsrb wd soft alarm status read back rnormalalarmx bit 5 multisel multisel read back r - - x bit 4 fs4rb fs4 read back r - - x bit 3 fs3rb fs3 read back r - - x bit 2 fs2rb fs2 read back r - - x bit 1 fs1rb fs1 read back r - - x bit 0 fs0rb fs0 read back r - - x i 2 c table: output control register control function bit 7 zclk_1 output control rw disable enable 1 bit 6 zclk_0 output control rw disable enable 1 bit 5 pciclk_f0 pci_stop# control rw stop disable stop enable 0 bit 4 pciclk_f1 pci_stop# control rw stop disable stop enable 0 bit 3 cpuclk8t0/c0 cpu_stop# control rw stop disable stop enable 1 bit 2 cpuclk8t1/c1 cpu_stop# control rw stop disable stop enable 1 bit 1 cpuclk8t0/c0 output control rw disable enable 1 bit 0 cpuclk8t1/c1 output control rw disable enable 1 type type see table1 : quad rom frequency selection table see table1 01 0 1 0pwd pwd 1 pwd pwd name type 1 0 byte 3 pin # - - - - - - - - name type byte 4 pin # - - - - - - - byte 5 pin # name - - - - - - - - name 9 42, 41 46, 45 13 14 10 byte 6 pin # 42, 41 46, 45
11 integrated circuit systems, inc. ICS952801 advance information 0719?01/22/03 i 2 c table: output control register control function bit 7 pciclk_f1 output control rw disable enable 1 bit 6 pciclk_f0 output control rw disable enable 1 bit 5 pciclk5 output control rw disable enable 1 bit 4 pciclk4 output control rw disable enable 1 bit 3 pciclk3 output control rw disable enable 1 bit 2 pciclk2 output control rw disable enable 1 bit 1 pciclk1 output control rw disable enable 1 bit 0 pciclk0 output control rw disable enable 1 i 2 c table: byte count register control function bit 7 bc7 rw - - 0 bit 6 bc6 rw - - 0 bit 5 bc5 rw - - 0 bit 4 bc4 rw - - 0 bit 3 bc3 rw - - 1 bit 2 bc2 rw - - 1 bit 1 bc1 rw - - 1 bit 0 bc0 rw - - 1 i 2 c table: watchdog timer register control function bit 7 wd7 rw - - 0 bit 6 wd6 rw - - 0 bit 5 wd5 rw - - 0 bit 4 wd4 rw - - 1 bit 3 wd3 rw - - 0 bit 2 wd2 rw - - 0 bit 1 wd1 rw - - 0 bit 0 wd0 rw - - 0 i 2 c table: vco control select bit & wd timer control register control function bit 6 wden watchdog enable r disable enable 0 bit 5 reserved reserved rw - - 0 bit 4 wd sf4 rw - - 0 bit 3 wd sf3 rw - - 0 bit 2 wd sf2 rw - - 0 bit 1 wd sf1 rw - - 0 bit 0 wd sf0 rw - - 1 type type byte 9 pin # name 1 0 disable 0 pwd pwd 1 01 0 enable pwd 14 type name 0 1 13 22 21 byte 7 pin # byte 8 pin # name 20 19 18 17 pwd - writing to this register will configure how many bytes will be read back, default is 0f = 15 bytes. - - - - - - - - these bits represent x*290ms the watchdog timer will wait before it goes to alarm mode. default is 16 x 290ms =4.64 seconds - - - - - - - byte 10 pin # bit 7 -m/nen m/n programming enable name type rw - - - - - - writing to these bit will configure the safe frequency as byte4bit 2, (7:4), byte 24bit(6:5) -
12 integrated circuit systems, inc. ICS952801 advance information 0719?01/22/03 i 2 c table: vco frequency control register control function bit 7 n div8 n divider bit 8 rw - - x bit 6 m div6 rw - - x bit 5 m div5 rw - - x bit 4 m div4 rw - - x bit 3 m div3 rw - - x bit 2 m div2 rw - - x bit 1 m div1 rw - - x bit 0 m div0 rw - - x i 2 c table: vco frequency control register control function bit 7 n div7 rw - - x bit 6 n div6 rw - - x bit 5 n div5 rw - - x bit 4 n div4 rw - - x bit 3 n div3 rw - - x bit 2 n div2 rw - - x bit 1 n div1 rw - - x bit 0 n div0 rw - - x i 2 c table: spread spectrum control register control function bit 7 ssp7 rw - - x bit 6 ssp6 rw - - x bit 5 ssp5 rw - - x bit 4 ssp4 rw - - x bit 3 ssp3 rw - - x bit 2 ssp2 rw - - x bit 1 ssp1 rw - - x bit 0 ssp0 rw - - x i 2 c table: spread spectrum control register control function bit 7 reserved reserved r - - 0 bit 6 reserved reserved r - - 0 bit 5 ssp13 rw - - x bit 4 ssp12 rw - - x bit 3 ssp11 rw - - x bit 2 ssp10 rw - - x bit 1 ssp9 rw - - x bit 0 ssp8 rw - - x 1 01 0 0 1 pwd pwd pwd 01 type byte 11 pin # name the decimal representation of m div (6:0) + 2 is equal to reference divider value. default at power up = latch-in or byte 0 rom table. - - - - - - - byte 12 pin # name - type - the decimal representation of n div (8:0) + 8 is equal to vco divider value. default at power up = latch-in or byte 0 rom table. - - - - - - - byte 13 pin # name type - these spread spectrum bits will program the spread pecentage. it is recommended to use ics spread % table for spread programming. - - - - - - - pwd - byte 14 pin # name type - - it is recommended to use ics spread % table for spread programming. - - - - -
13 integrated circuit systems, inc. ICS952801 advance information 0719?01/22/03 i 2 c table: output divider control register control function bit 7 reserved reserved rw - - x bit 6 reserved reserved rw - - x bit 5 reserved reserved rw - - x bit 4 reserved reserved rw - - x bit 3 cpu div3 rw x bit 2 cpu div2 rw x bit 1 cpu div1 rw x bit 0 cpu div0 rw x 01pwd - - - type - byte 15 pin # name - cpu divider ratio can be configured via these 4 bits individually. see table 5: divider ratio combination table - - - table 5: cpu divider ratio combination table bit00011011msb 1248 00 0000 2 0100 4 1000 8 1100 16 01 0001 3 0101 6 1001 12 1101 24 10 0010 5 0110 10 1010 20 1110 40 11 0011 7 0111 14 1011 28 1111 56 lsb address div address div address div address div divider (3:2) divider (1:0) i 2 c table: output divider control register control function bit 7 reserved reserved rw - - x bit 6 reserved reserved rw - - x bit 5 reserved reserved rw - - x bit 4 reserved reserved rw - - x bit 3 reserved reserved rw - - x bit 2 reserved reserved rw - - x bit 1 reserved reserved rw - - x bit 0 reserved reserved rw - - x i 2 c table: output divider control register control function bit 7 reserved reserved rw - - x bit 6 reserved reserved rw - - x bit 5 reserved reserved rw - - x bit 4 cpuinv cpu phase invert rw default inverse x bit 3 reserved reserved rw - - x bit 2 reserved reserved rw - - x bit 1 reserved reserved rw - - x bit 0 reserved reserved rw - - x pwd - - - type 0 1 - byte 16 pin # name - - - - 01pwd - byte 17 pin # name type - - - - - - -
14 integrated circuit systems, inc. ICS952801 advance information 0719?01/22/03 i 2 c table: group skew control register control function bit 7 reserved reserved rw - - x bit 6 reserved reserved rw - - x bit 5 reserved reserved rw - - x bit 4 reserved reserved rw - - x bit 3 reserved reserved rw - - x bit 2 reserved reserved rw - - x bit 1 reserved reserved rw - - x bit 0 reserved reserved rw - - x i 2 c table: group skew control register control function bit 7 zclkskw1 rw 0 bit 6 zclkskw0 rw 0 bit 5 reserved reserved rw - - 0 bit 4 reserved reserved rw - - 0 bit 3 agpskw1 rw 0 bit 2 agpskw0 rw 0 bit 1 reserved reserved rw - - 0 bit 0 reserved reserved rw - - 0 i 2 c table: group skew control register control function bit 7 pci_fskw1 rw 0 bit 6 pci_fskw0 rw 0 bit 5 reserved reserved rw - - 0 bit 4 reserved reserved rw - - 0 bit 3 pciskw1 rw 0 bit 2 pciskw0 rw 0 bit 1 reserved reserved rw - - 0 bit 0 reserved reserved rw - - 0 pin # pwd - - - name type 0 1 - byte 18 01 - - - - - byte 19 pin # name pwd - - - type see table 6: 4-steps skew programming table - - - - pwd - byte 20 pin # name type - - 01 - - - - - see table 6: 4-steps skew programming table see table 6: 4-steps skew programming table see table 6: 4-steps skew programming table cpu-zclk skew control cpu-agp skew control cpu-pci_f skew control cpu-pci skew control table 6: 4-steps skew programming table 4 step 0 1 lsb 0 0ps 250ps - 1 500ps 750ps - msb ---
15 integrated circuit systems, inc. ICS952801 advance information 0719?01/22/03 i 2 c table: slew rate control register pin # name control function type 0 1 pwd bit 7 24/48slw1 rw - - 0 bit 6 24/48slw0 rw - - 0 bit 5 agpslw1 rw - - 0 bit 4 agpslw0 rw - - 0 bit 3 zclkslw1 rw - - 0 bit 2 zclkslw0 rw - - 0 bit 1 refslw1 rw - - 0 bit 0 refslw0 rw - - 0 i 2 c table: slew rate control register control function bit 7 sdslw1 rw - - 0 bit 6 sdslw0 rw - - 0 bit 5 agpclk1 output control rw disable enable 1 bit 4 agpclk0 output control rw disable enable 1 bit 3 pci_fslw1 rw - - 0 bit 2 pci_fslw0 rw - - 0 bit 1 pcislw1 rw - - 0 bit 0 pcislw0 rw - - 0 i 2 c table: output control register control function bit 7 reserved reserved rw - - 0 bit 6 sel24_48 24mhz or 48mhz rw 48mhz 24mhz 1 bit 5 reserved reserved rw - - 1 bit 4 48mhz output control rw disable enable 1 bit 3 24_48mhz output control rw disable enable 1 bit 2 ref2 output control rw disable enable 1 bit 1 ref1 output control rw disable enable 1 bit 0 ref0 output control rw disable enable 1 i 2 c table: reserved register control function bit 7 reserved reserved rw - - 0 bit 6 fs6 freq select bit 6 rw 0 bit 5 fs5 freq select bit 5 rw 0 bit 4 reserved reserved rw - - 0 bit 3 reserved reserved rw - - 0 bit 2 ss_sel ss scheme select1 rw 0 bit 1 ss_sel ss scheme select1 rw 0 bit 0 reserved reserved rw - - 0 byte 21 - - - - 24/48 slew rate control agp slew rate control - - - - zclk slew rate control ref slew rate control pwd - - byte 22 pin # name type 1 0 34 35 - - - - 1 0pwd - byte 23 pin # name type 4 3 2 - - 30 29 - - - - - see table 1 - pwd - byte 24 pin # name type see table 2: spread spectrum selection table pci slew rate control pci_f slew rate control sd slew rate control 01
16 integrated circuit systems, inc. ICS952801 advance information 0719?01/22/03 table2: spread spectrum select table ss1 ss0 ( b y te 24 bit 2 ) ( b y te 24 bit 1 ) 000.35% 010.50% 100.75% 112.50% for spreadable frequency only
17 integrated circuit systems, inc. ICS952801 advance information 0719?01/22/03 absolute maximum ratings stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operation al sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect p roduct reliability. core supply voltage . . . . . . . . . . . . . . . . . . . . . . . 4.6 v i/o supply voltage . . . . . . . . . . . . . . . . . . . . . . . . 3.6v logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd ?0.5 v to v dd +0.5 v ambient operating temperature . . . . . . . . . . . . . 0c to +70c storage temperature . . . . . . . . . . . . . . . . . . . . . . ?65c to +150c case temperature . . . . . . . . . . . . . . . . . . . . . . . . 115c electrical characteristics - input/supply/common output parameters t a = 0 - 70c; supply voltage v dd = 3.3 v +/-5% (unless otherwise stated) parameter symbol conditions min typ max units input high voltage v ih 2v dd + 0.3 v input low voltage v il v ss - 0.3 0.8 v input high current i ih v in = v dd 5ma input low current i il1 v in = 0 v; inputs with no pull-up resistors -5 ma input low current i il2 v in = 0 v; inputs with pull-up resistors -200 ma operating supply current i dd(op) c l = 0 pf; select @ 100mhz 180 ma power down supply current i ddpd c l = 0 pf; with input address to vdd or gnd 40 ma input frequency f i v dd = 3.3 v; 11 16 mhz c in logic inputs 5 pf c inx x1 & x2 pins 27 45 pf transition time 1 t trans to 1st crossing of target freq. 3 ms clk stabilization 1 t stab from v dd = 3.3 v to 1% target freq. 3 ms skew 1 t cpu-pci v t = 1.5 v 1.5 4 ns 1 guaranteed by design, not 100% tested in production. input capacitance 1
18 integrated circuit systems, inc. ICS952801 advance information 0719?01/22/03 electrical characteristics - zclk t a = 0 - 70c; vdd=3.3v +/-5%; c l = 10-30 pf (unless otherwise specified) parameter symbol conditions min typ max units output frequency f o1 mhz output impedance r dsp1 1 v o = v dd *(0.5) 12 55 ? output high voltage v oh 1 i oh = -1 ma 2.4 v output low voltage v ol 1 i ol = 1 ma 0.55 v output high current i oh 1 v oh@min = 1.0 v, v oh@max = 3.135 v -33 -33 ma output low current i ol 1 v ol @min = 1.95 v, v ol @max = 0.4 v 30 38 ma rise time t r1 1 v ol = 0.4 v, v oh = 2.4 v 0.5 2 ns fall time t f1 1 v oh = 2.4 v, v ol = 0.4 v 0.5 2 ns duty cycle d t1 1 v t = 1.5 v 45 55 % skew t sk1 1 v t = 1.5 v 250 ps jitter t jcyc-cyc 1 v t = 1.5 v 3v66 250 ps electrical characteristics - agpclk, zclk t a = 0 - 70c; vdd=3.3v +/-5%; c l = 10-30 pf (unless otherwise specified) parameter symbol conditions min typ max units output frequency f o1 mhz output impedance r dsp1 1 v o = v dd *(0.5) 12 55 ? output high voltage v oh 1 i oh = -1 ma 2.4 v output low voltage v ol 1 i ol = 1 ma 0.55 v output high current i oh 1 v oh@min = 1.0 v, v oh@max = 3.135 v -33 -33 ma output low current i ol 1 v ol @min = 1.95 v, v ol @max = 0.4 v 30 38 ma rise time t r1 1 v ol = 0.4 v, v oh = 2.4 v 0.5 2 ns fall time t f1 1 v oh = 2.4 v, v ol = 0.4 v 0.5 2 ns duty cycle d t1 1 v t = 1.5 v 45 55 % skew t sk1 1 v t = 1.5 v 250 ps jitter t jcyc-cyc 1 v t = 1.5 v 3v66 250 ps electrical characteristics - pciclk t a = 0 - 70c; v dd = 3.3 v,+/-5%; c l = 30 pf parameter symbol conditions min typ max units output high voltage v oh1 i oh = -18 ma 2.1 v output low voltage v ol1 i ol = 9.4 ma 0.4 v output high current i oh1 v oh = 2.0 v -22 ma output low current i ol1 v ol = 0.8 v 16 57 ma rise time 1 t r1 v ol = 0.4 v, v oh = 2.4 v 2 ns fall time 1 t f1 v oh = 2.4 v, v ol = 0.4 v 2 ns duty cycle 1 d t1 v t = 1.5 v 45 55 % skew 1 t sk1 v t = 1.5 v 500 ps t j c y c-c y c 1 v t = 1.5 v 500 ps t jabs1 v t = 1.5 v 500 ps 1 guaranteed by design, not 100% tested in production. jitter
19 integrated circuit systems, inc. ICS952801 advance information 0719?01/22/03 electrical characteristics - 48mhz, 24_48mhz t a = 0 - 70c; vdd=3.3v +/-5%; c l = 10-20 pf (unless otherwise specified) parameter symbol conditions min typ max units output impedance r dsp1 1 v o = v dd *(0.5) 20 60 ? output high voltage v oh 1 i oh = -1 ma 2.4 v output low voltage v ol 1 i ol = 1 ma 0.4 v v oh@min = 1.0 v -29 v oh@max = 3.135 v -23 ma v ol @min = 1.95 v 29 v ol @max = 0.4 v 27 ma rise time t r1 1 v ol = 0.4 v, v oh = 2.4 v 0.5 1 ns fall time t f1 1 v oh = 2.4 v, v ol = 0.4 v 0.5 1 ns duty cycle d t1 1 v t = 1.5 v 45 55 % jitter t jcyc-cyc 1 v t = 1.5 v 350 ps 1 guaranteed by design, not 100% tested in production. output high current i oh 1 output low current i ol 1 electrical characteristics - ref t a = 0 - 70c; v dd = 3.3 v , +/-5%; c l = 10 - 20 pf (unless otherwise stated) parameter symbol conditions min typ max units output high voltage v oh5 i oh = -12 ma 2.6 v output low voltage v ol5 i ol = 9 ma 0.4 v output high current i oh5 v oh = 2.0 v -22 ma output low current i ol5 v ol = 0.8 v 16 ma rise time 1 t r5 v ol = 0.4 v, v oh = 2.4 v 4 ns fall time 1 t f5 v oh = 2.4 v, v ol = 0.4 v 4 ns duty cycle 1 d t5 v t = 1.5 v 45 55 % t j c y c-c y c5 v t = 1.5 v 1000 ps t jabs5 v t = 1.5 v 800 ps jitter 1
20 integrated circuit systems, inc. ICS952801 advance information 0719?01/22/03 electrical characteristics - cpuclk t a = 0 - 70o c; v dd = 3.3 v +/-5%; c l = 20 pf (unless otherwise stated) parameter symbol conditions min typ max units output impedance z o v o = v x 15 55 w output high voltage v oh2b 11.2v output low voltage v ol2b 0.4 v output low current i ol2b v ol = 0.3 v 18 ma rise edge rate 1 measured from 20-80% 2 7 v/ns fall edge rate 1 measured from 80-20% 2 7 v/ns v diff differential voltage, measured @ the hammer test load (single-ended measurement) 0.4 2.3 v dv di ff change in v di ff_dc magnitude, measured @ the hammer test load (single-ended measurement) -150 150 mv v cm common mode voltage, measured @ the hammer test load (single-ended measurement) 1.05 1.45 v dv cm change in common mode voltage, measured @ the hammer test load (single- ended measurement) -200 200 mv duty cycle 1 d t2b v t = 50% 45 53 % jitter, cycle-to-cycle 1 t j c y c-c y c2b v t = v x 0 200 ps notes: 1 - guaranteed by design, not 100% tested in production. 3 - vpullup ( external ) = 1.5v, min = vpullup ( external ) /2-150mv; max=(vpullup ( external ) /2)+150mv 2 - v di f specifies the minimum input differential voltages (v tr -v cp ) required for switching, where v tr is the "true" input level and v cp is the "complement" input level.
21 integrated circuit systems, inc. ICS952801 advance information 0719?01/22/03 fig. 1 shared pin operation - input/output pins the i/o pins designated by (input/output) serve as dual signal functions to the device. during initial power-up, they act as input pins. the logic level (voltage) that is present on these pins at this time is read and stored into a 5-bit internal data latch. at the end of power-on reset, (see ac characteristics for timing values), the device changes the mode of operations for these pins to an output function. in this mode the pins produce the specified buffered clocks to external loads. to program (load) the internal configuration register for these pins, a resistor is connected to either the vdd (logic 1) power supply or the gnd (logic 0) voltage potential. a 10 kilohm (10k) resistor is used to provide both the solid cmos programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. via to vdd clock trace to load series term. res. programming header via to gnd device pad 2k 8.2k figure 1 shows a means of implementing this function when a switch or 2 pin header is used. with no jumper is installed the pin will be pulled high. with the jumper in place the pin will be pulled low. if programmability is not necessary, than only a single resistor is necessary. the programming resistors should be located close to the series termination resistor to minimize the current loop area. it is more important to locate the series termination resistor close to the driver than the programming resistor.
integrated circuit systems, inc. ICS952801 advance information 22 0719?01/22/03 ordering information ICS952801 y ft designation for tape and reel packaging package type f = ssop revision designator (will not correlate with datasheet revision) device type prefix ics = standard device example: ics xxxxx y f - t index area index area 1 2 n d h x 45 e1 e seating plane seating plane a1 a e - c - b .10 (.004) c .10 (.004) c c l min max min max a 2.41 2.80 .095 .110 a1 0.20 0.40 .008 .016 b 0.20 0.34 .008 .0135 c 0.13 0.25 .005 .010 d e 10.03 10.68 .395 .420 e1 7.40 7.60 .291 .299 e h 0.38 0.64 .015 .025 l 0.50 1.02 .020 .040 n

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